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1. general description the DAC1627D1G25 is a high-speed 16-bit du al channel digital-to-analog converter (dac) with selectable 2, 4 and 8 interpolating filters opti mized for multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 gsps. supplied from a 3.3 v and a 1.8 v source, the DAC1627D1G25 integrates a differential scalable output current up to 31.8 ma. the DAC1627D1G25 is capable of meeting multi-carrier gsm sp ecifications. for example, with an output frequency of 150 mh z and a dac clock frequency of 1.22 gsps the full-scale dynamic range is: ? sfdr rbw = 85 dbc (bandwidth = 250 mhz) ? imd3 = 85 dbc the serial peripheral interface (spi) prov ides full control of the DAC1627D1G25. the DAC1627D1G25 integrates a low voltage dif ferential signaling (lvds) double data rate (ddr) receiver interf ace, with an on-chip 100 termination. the lvds ddr interface accepts a multiplex input data stream such as interleaved or folded. an internal lvds input auto-calibration ensures the ro bustness and stabilit y of the interface. digital on-chip modulation converts the complex i and q inputs from baseband to if. the mixer frequency is set by a 40-bit numerically controlled oscillator (nco). high resolution internal gain, phase and offset control provide outsta nding image and local oscillator (lo) signal rejection at the system analog modulator output. an inverse (sin x) / x function ensures a cont rolled flatness 0.5 db for high bandwidths at the dac output. multiple device synchronization allows synchronization of the outputs of multiple dac devices. mds guarantees a maximum skew of one output clock period between several devices. the DAC1627D1G25 includes a very low noise capacitor-free integrated phase-locked loop (pll) multiplier which generates a dac clock rate from the lvds clock rate. the DAC1627D1G25 is available in a hvqfn72 package (10 mm 10 mm). DAC1627D1G25 dual 16-bit dac, lvds interface, up to 1.25 gsps, x2, x4 and x8 interpolating rev. 1 ? 29 april 2011 objective data sheet
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 2 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 2. features and benefits 3. applications ? wireless infrastructure: mg_gsm, lte, wimax, gsm, cdma, wcdma, td-scdma ? communication: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? broadband wireless systems ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information ? dual 16-bit resolution ? synchronization of multiple dac devices ? 1.25 gsps maximum update rate ? 3 or 4 wires mode spi interface ? selectable 2, 4 and 8 interpolation filters ? differential scalable output current from 6.95 ma to 31.8 ma ? very low noise capacitor-free integrated phase-locked loop (pll) ? external analog offset control (10-bit auxiliary dacs) ? embedded numerically controlled oscillator (nco) with 40-bit programmable frequency ? high resolution internal digital gain and offset control to support high performance iq-modulator image rejection ? embedded complex modulator ? internal phase correction ? 1.8 v and 3.3 v power supplies ? inverse (sin x) / x function ? lvds ddr compatible input interface with on-chip 100 terminations ? power-down mode and sleep mode; 5-bit nco low power mode ? lvds ddr input clock up to 312.5 mhz ? on-chip 1.25 v reference ? lvds or lvpecl compatible dac clock ? industrial temperature range ? 40 c to +85 c ? interleaved or folded i and q data input mode ? 72 pins small form factor hvqfn package table 1. ordering information type number package name description version DAC1627D1G25 hvqfn72 plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 10 0.85 mm sot813-3
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 3 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating 5. block diagram fig 1. block diagram 001aan827 ioutbp ioutbn ioutap ioutan auxap auxan sin cos + offset control dac b x sin x gapout vires + x sin x 10-bit analog gain control 10-bit analog gain control phase comp phase comp 10-bit offset control nco 40-bit frequency setting 16-bit phase adjustment 10-bit offset control ref. bandgap and biasing dac a aux. dac auxbp auxbn aux. dac x2 fir 2 x2 fir 1 multi-dac synchronization x2 fir 2 x2 fir 3 x2 fir 3 x2 fir 1 clock generator/pll dcmsu cdi spi sdo sdio scs_n sclk mds coarse phase compensation digital gain/offset lvds ddr/ dif clkp ldclkn ldclkp ld(15)n to ld(0)n ld(15)p to ld(0)p alignn alignp clkn mdsp mdsn reset_n dac1627d complex modulator + + + - 16 16
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 4 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration 001aan828 DAC1627D1G25 transparent top view ld[4]n ld[12]n ld[11]p ld[3]p ld[12]p ld[3]n ld[13]n ld[2]p ld[13]p ld[2]n v ddd(1v8) v ddd(1v8) ld[14]n ld[1]p ld[14]p ld[1]n ld[15]n ld[0]p ld[15]p ld[0]n alignn io1 alignp io0 tm sdo mdsn sdio mdsp sclk clkn scs_n ld[10]p ld[10]n ld[9]p ld[9]n ld[8]p ld[8]n v ddd(1v8) lckp lckn gnd_dp ld[7]p ld[7]n ld[6]p ld[6]n ld[5]p ld[5]n ioutan ioutap v dda(1v8)_d v dda(3v3) auxap auxan v dda(1v8)_p2 gapout vires v dda(1v8)_p1 auxbn auxbp v dda(3v3) v dda(1v8)_d ioutbp ioutbn ld[11]n ld[4]p clkp reset_n v ddd(1v8) v ddd(1v8) v dda(1v8)_d v dda(1v8)_d 17 18 38 37 16 39 15 40 14 41 13 42 12 43 11 44 10 45 9 46 8 47 7 48 6 49 5 50 4 51 3 52 2 1 53 54 71 72 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 terminal 1 index area table 2. pin description symbol pin type [1] description clkp 1 i dac clock positive input clkn 2 i dac clock negative input mdsp 3 io multi-device synchro nization positive signal mdsn 4 io multi-device synchronization negative signal tm 5 i test mode selection (connect to gnd) alignp 6 i positive input for data alignment alignn 7 i negative input for data tanglement ld[15]p 8 i lvds positive input bit 15 [2] ld[15]n 9 i lvds negative input bit 15 [2]
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 5 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating ld[14]p 10 i lvds positive input bit 14 [2] ld[14]n 11 i lvds negative input bit 14 [2] v ddd(1v8) 12 p 1.8 v digital power supply ld[13]p 13 i lvds positive input bit 13 [2] ld[13]n 14 i lvds negative input bit 13 [2] ld[12]p 15 i lvds positive input bit 12 [2] ld[12]n 16 i lvds negative input bit 12 [2] ld[11]p 17 i lvds positive input bit 11 [2] ld[11]n 18 i lvds negative input bit 11 [2] v ddd(1v8) 19 p 1.8 v digital power supply ld[10]p 20 i lvds positive input bit 10 [2] ld[10]n 21 i lvds negative input bit 10 [2] ld[9]p 22 i lvds positive input bit 9 [2] ld[9]n 23 i lvds negative input bit 9 [2] ld[8]p 24 i lvds positive input bit 8 [2] ld[8]n 25 i lvds negative input bit 8 [2] v ddd(1v8) 26 p 1.8 v digital power supply lckp 27 i lvds positive data clock input lckn 28 i lvds negative data clock input gnd_dp 29 g connect to ground ld[7]p 30 i lvds positive input bit 7 [2] ld[7]n 31 i lvds negative input bit 7 [2] ld[6]p 32 i lvds positive input bit 6 [2] ld[6]n 33 i lvds negative input bit 6 [2] ld[5]p 34 i lvds positive input bit 5 [2] ld[5]n 35 i lvds negative input bit 5 [2] v ddd(1v8) 36 p 1.8 v digital power supply ld[4]p 37 i lvds positive input bit 4 [2] ld[4]n 38 i lvds negative input bit 4 [2] ld[3]p 39 i lvds positive input bit 3 [2] ld[3]n 40 i lvds negative input bit 3 [2] ld[2]p 41 i lvds positive input bit 2 [2] ld[2]n 42 i lvds negative input bit 2 [2] v ddd(1v8) 43 p 1.8 v digital power supply ld[1]p 44 i lvds positive input bit 1 [2] ld[1]n 45 i lvds negative input bit 1 [2] ld[0]p 46 i lvds positive input bit 0 [2] ld[0]n 47 i lvds negative input bit 0 [2] io1 48 io io port bit 1 io0 49 io io port bit 0 sdo 50 o spi data output table 2. pin description ?continued symbol pin type [1] description
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 6 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating [1] p: power supply; g: ground; i: input; o: output. [2] the lvds input data bus order can be reversed and each element can be swapped between p and n using dedicated registers (see table 86 , ta b l e 8 7 and table 88 ). 7. limiting values sdio 51 io spi data input/output sclk 52 i spi clock scs_n 53 i spi chip se lect (active low) reset_n 54 i general reset (active low) v dda(1v8)_d 55 p 1.8 v analog power supply (dac core) ioutbn 56 o complementary dac b output current ioutbp 57 o dac b output current v dda(1v8)_d 58 p 1.8 v analog power supply (dac core) v dda(3v3) 59 p 3.3 v analog power supply auxbp 60 o auxiliary dac b output current auxbn 61 o complementary auxiliary dac b output current v dda(1v8)_p1 62 p 1.8 v analog power supply (pll) vires 63 io dac biasing resistor gapout 64 io band gap input/output voltage v dda(1v8)_p2 65 p 1.8 v analog power supply (pll) auxan 66 o complementary auxiliary dac a output current auxap 67 o auxiliary dac a output current v dda(3v3) 68 p 3.3 v analog power supply v dda1v8_d 69 p 1.8 v analog power supply (dac core) ioutap 70 o dac a output current ioutan 71 o complementary dac a output current v dda(1v8)_d 72 p 1.8 v analog power supply (dac core) gnd h g ground (exposed die pad) table 2. pin description ?continued symbol pin type [1] description table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v ddd(1v8) digital supply voltage (1.8 v) ? 0.5 +2.5 v v dda(1v8) analog supply voltage (1.8 v) [1] ? 0.5 +2.5 v v i input voltage input pins referenced to gnd ? 0.5 v v o output voltage pins ioutap, ioutan, ioutbp, ioutbn, auxap, auxan, auxbp and auxbn referenced to gnd ? 0.5 +4.6 v
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 7 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating [1] the analog 1.8 v power supply must be c onnected to pins vdda1v8_d, vdda1v8_p1, and vdda1v8_p2. 8. thermal characteristics [1] value for six layers board in still ai r with a minimum of 49 thermal vias. t stg storage temperature ? 55 +150 c t amb ambient temperature ? 40 +85 c t j junction temperature ? 40 +125 c table 3. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 16.2 k/w r th(j-c) thermal resistance from junction to case [1] 6.7 k/w
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 8 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 9. characteristics table 5. characteristics v dda(1v8) =1.8v; v ddd(1v8) =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 22 ; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit v dda(3v3) analog supply voltage (3.3 v) c 3.15 3.3 3.45 v v ddd(1v8) digital supply voltage (1.8 v) c1.7 1.8 1.9 v v dda(1v8) analog supply voltage (1.8 v) c [2] 1.7 1.8 1.9 v i dda(3v3) analog supply current (3.3 v) aux dac on c 63 ma i ddd(1v8) digital supply current (1.8 v) f s = 983.04 67; 4 interpolation; no nco; mds on c 520 ma f s = 620 msps; 2 interpolation; nco on; no mds c 440 ma i dda(1v8) analog supply current (1.8 v) f s = 983.04 msps; 1 v (p-p) c [2] 210 ma f s = 620 msps; 1 v (p-p) c 210 ma p tot total power dissipation f s = 1228.8 msps; 4 interpolation; nco on; mds off c - 1770 - mw f s = 983.04 msps; 4 interpolation; 5-bit nco; mds off c - 1530 - mw f s = 983.04 msps; 4 interpolation; nco off; mds off c- - mw f s = 737.28 msps; 4 interpolation; 5-bit nco; mds off c - 1540 - mw f s = 620 msps; 2 interpolation; 40-bit nco; mds off -1400-mw full power-down c - 1.2 - mw clock inputs (pins clkp, clkn) v i(clk)dif differential clock input voltage peak-to-peak c 200 - 2000 mv r i input resistance d - - m c i input capacitance d - - pf digital inputs (pins ld[15]p to ld[0]p , ld[15]n to ld[0]n, lckp and lckn) v i input voltage | v gpd | < 50 mv [3] c 825 - 1575 mv v idth input differential threshold voltage | v gpd | < 50 mv [3] c ? 100 - +100 mv
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 9 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating r i input resistance d - 100 - c i input capacitance d - - pf digital inputs/outputs (pins mdsn, mdsp) v o(dif)(p-p) peak-to-peak differential output voltage c- 600 - mv c o(l) output load capacitance between gnd and pin mdsn or mdsp d- - pf c i input capacitance between gnd and pin mdsn or mdsp d - - pf r i input resistance d - 100 - v i input voltage | v gpd | < 50 mv [3] c 825 - 1575 mv v idth input differential threshold voltage | v gpd | < 50 mv [3] c ? 100 - +100 mv digital inputs/outputs (pins sdo, sdio, sclk, scs_n, reset_n) v il low-level input voltage cgnd- 0.3v dd(1v8) v v ih high-level input voltage c0.7v dd(1v8) -v dd(1v8) v v ol low-level output voltage pins sdo and sdio c 0 - v v oh high-level output voltage pins sdo and sdio c - v dd(1v8) v i il low-level input current v il = v i - - a i ih high-level input current v ih = v i - - a c i input capacitance d - - pf analog outputs (pins iout ap, ioutan, ioutbp, ioutbn) i o(fs) full-scale output current controlled by the analog gain registers (see ta b l e 4 6 to table 49 ) d 6.19 - 31.8 ma default value d - 20 - ma v o output voltage compliance range d - v dda(3v3) v v o(cm) common-mode output voltage d- 2.8 - v r o output resistance d - 250 - k c o output capacitance d- 3 - pf n dac(mono) dac monotonicity guaranteed d - - bits table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd(1v8) =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 22 ; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 10 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating e o offset error variation d - - ppm/ c e g gain error variation d - - ppm/ c reference voltage output (pin gapout) v o(ref) reference output voltage t amb =+25 c i 1.25 v i o(ref) reference output current 1.25 v external voltage d - 40 - a v o(ref) reference output voltage variation c - - ppm/ c analog auxiliary outputs (pins auxap, auxan, auxbp and auxbn) i o(fs) full-scale output current auxiliary dac a; differential outputs i- 2.2 - ma auxiliary dac b; differential outputs i- 2.2 - ma v o(aux) auxiliary output voltage compliance range c 0 - 2 v n dac(aux)mono auxiliary dac monotonicity guaranteed d - 10 - bits lvds input timing f data data rate input; 2 interpolation c - 312.5 mhz input; 4 interpolation c - 312.5 mhz input; 8 interpolation c - 156.25 mhz t sk(clk-d) skew time from clock to data input c ? - + ps dac output timing f s sampling rate c - - 1250 msps t s settling time to 0.5 lsb d - 20 - ns internal pll timing f s sampling rate c - - 1000 msps 40-bit nco frequency range; f s = 1000 msps f nco nco frequency two?s complement coding reg value = 8000000000h d - ? 500 - mhz reg value = ffffffffffh d - ? 0.9095 - mhz reg value = 0000000000h d - 0 - hz reg value = 0000000001h d - +0.9095 - mhz reg value = 7fffffffffh d - +499.99909 - mhz f step step frequency d - 0.9095 - mhz table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd(1v8) =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 22 ; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 11 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating low power nco frequency range; f s = 1000 mhz f nco nco frequency two?s complement coding reg value = f8000000000h d - ? 500 - mhz reg value = f8000000000h d - ? 31.25 - mhz reg value = 00000000000h d - 0 - hz reg value = 08000000000h d - +31.25 - mhz reg value = 7fffffffffh d - +468.75 - mhz f step step frequency d - 31.25 - mhz dynamic performance sfdr spurious-free dynamic range f data = 307.2 mhz; f s = 1228.8 msps; bw = f s /2 f o =20mhz at ? 1 dbfs; i - 83 - dbc f data = 245.76 mhz; f s = 983.04 msps; bw = f s /2 f o =20mhz at ? 1dbfs i - 85 - dbc sfdr rbw restricted bandwidth spurious-free dynamic range f data = 245.76 mhz; f s = 983.04 msps; f o =150mhz bw = 100 mhz i - 90 - dbc bw = 180 mhz i - - dbc f data = 307.2 mhz; f s = 1228.8 msps; f o =210mhz bw = 100 mhz i - - dbc bw = 180 mhz i - - dbc imd3 third-order intermodulation distortion f data = 245.76 mhz; f s = 983.04 msps; f o1 =20mhz; f o2 =21mhz; 4 interpolation; output level = ? 1dbfs i- 93 - dbc f data = 245.76 mhz; f s = 983.04 msps; f o1 = 152 mhz; f o2 = 155.1 mhz; f s = 1228.8 mhz; 4 interpolation; output level = ? 1dbfs i- 85 - dbc table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd(1v8) =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 22 ; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 12 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] v dda(1v8)_d , v dda(1v8)_p1 and v dda(1v8)_p2 must be connected to the same 1.8 v analog power supply. it is recommended to use dedicated filters for the three power pins. [3] | v gpd | represents the ground potential difference voltage. this voltage is the result of current flowing through the finite resistanc e and the inductance between the receiver and the driver circuit ground voltages. 10. application information 10.1 general description the DAC1627D1G25 is a dual 16-bit dac oper ating up to 1250 msps. each dac consists of a segmented architecture, comprising a 6-bit thermometer sub-dac and a 10-bit binary weighted sub-dac. a maximum input lvds ddr data rate of up to 312.5 mhz and a maximum output sampling rate of 1250 msps ensure more fl exibility for wide bandwid th and multi-carrier systems. the internal 40-bit nco of th e DAC1627D1G25 simplifies the frequency selection of the system. the DAC1627D1G25 provides 2, 4 or 8 interpolation filters that are very useful for removing the undesired images. each dac generates two complementary current outputs on pins ioutap and ioutan and pins ioutbp and ioutbn. these outputs provide a full-scale output current (i o(fs) ) of up to 31.8 ma. an internal reference is available for the reference current which is externally adjustable using pin vires. high resolution internal gain, phase and offset control provide outstanding image and local oscillator (lo) signa l rejection at the system analog modulator output. multiple device synchronization enables synchronization of the outputs of multiple dac devices. mds guarantees a maximum skew of one output clock period between several devices. all functions can be set using an spi interface. acpr adjacent channel power ratio f s = 1228.8 msps; 4 interpolation; f o =210mhz 1 carrier; bw = 5 mhz d - 77 - dbc 2 carriers; bw = 10 mhz d - 73 - dbc 4 carriers; bw = 20 mhz d - 72 - dbc nsd noise spectral density f s = 983.04 msps; 4 interpolation; f o =20mhzat ? 1dbfs d - -164 - dbm/hz f s = 983.04 msps; 4 interpolation; f o =153.6mhzat ? 1dbfs d - -161 - dbm/hz table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd(1v8) =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 22 ; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 13 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.2 serial periphera l interface (spi) 10.2.1 protocol description the DAC1627D1G25 serial interface is a synchronous serial communication port ensures easy interface with many industry microprocessor s. it provides access to the registers that define the operating modes of the chip in both write and read mode. this interface can be configured as a 3-wire type (pin sdio as bidirectional pin) or 4-wire type (pins sdio and sdo as unidirectional pi ns, input and output port respectively). in both configurations, sclk acts as the serial clock and scs_n as the serial chip select. figure 3 shows the spi protocol. each read/writ e operation is followed by an scs_n signal and enabled by a low assertion to drive the chip with two to five bytes, depending on the content of the instruction byte (see ta b l e 7 ). r/w indicates the mode access (see ta b l e 6 ) ta b l e 7 shows the number of bytes to be transferred. n1 and n0 indicate the number of bytes transferred after the instruction byte. a[4:0] indicates which register is being ad dressed. if a multiple transfer occurs, this address concerns the first register. next are those which follow directly in a decreasing order (see ta b l e 2 3 , ta b l e 5 5 and ta b l e 7 9 ). fig 3. spi protocol 001aan829 reset_n (optional) scs_n sclk sdio sdo (optional) r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 6. read or write mode access description r/w description 0 write mode operation 1 read mode operation table 7. number of bytes to be transferred n1 n0 number of bytes transferred 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 14 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating the DAC1627D1G25 incorporates more than the 32 spi registers allowed by the address value a[4:0]. it uses three spi register pages (page_00, page_01, and page_0a), each containing 32 registers. the 32 nd register of each page indicates which page is currently addressed (00h, 01h or 0ah). 10.2.2 spi timing description the spi interface can operate at a frequency up to 15 mhz. the spi timings are shown in figure 4 . the spi timing characteristics are given in ta b l e 8 . 10.3 power-on sequence there are three steps for the power-on sequence (see figure 5 ): 1. the board is power-on. at the turn-on time, all DAC1627D1G25 supplies have reached their specification ranges. 2. at least 1 s after the turn-on time pin reset_n must be released. fig 4. spi timing diagram table 8. spi timing characteristics symbol parameter min typ max unit f sclk sclk frequency - - 25 mhz t w(sclk) sclk pulse width 30 - - ns t su(scs_n) scs_n set-up time 20 - - ns t h(scs_n) scs_n hold time 20 - - ns t su(sdio) sdio set-up time 10 - - ns t h(sdio) sdio hold time 5 - - ns t w(reset_n) reset_n pulse width 30 - - ns 001aan830 50 % t w(reset_n) t su(scs_n) t su(sdio) t h(sdio) t h(scs_n) t w(sclk) 50 % reset_n (optional) scs_n sclk sdio 50 % 50 %
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 15 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 3. when the dac clock and lvds clock are stable, the spi configuration is sent to the DAC1627D1G25. writing 0 in bits rst_ dclk and rst_lclk of the register main_cntrl (see ta b l e 8 0 ) starts the automatic calibration. 30 s after this calibration, the DAC1627D1G25 is operational. 10.4 lvds data input format (dif) block the data input formatting (dif) block captures and resynchronizes data on the lvds bus with its own lclkp/lclkn clock. each lvds input buffer has an internal resistance of 100 , so an external resistor is not required. the dif block includes two sub-blocks: ? ldvs receiver: provides high flexibility for the lvds interf ace, especially for th e pcb layout and the control of the input port polarity and the input port mapping. ? data format block: enables the adaptation, which ensures the support of several data encoding modes. 10.4.1 input port polarity the polarity of each individual lvds input (l d[15]p to ld[0]p and ld[15]n to ld[0]n) can be changed, ensuring a much easier pcb lay out design. the input polarity is controlled with bits ld_pol[7:0] in register ld_pol_lsb (see ta b l e 8 6 ) and bits ld_pol[15:8] in register ld_pol_msb (see ta b l e 8 7 ). fig 5. power-on sequence 001aan810 spi bus write dac configuration start clock calibration time reset_n t on power in specification range t spi_start t rst power supplies fig 6. lvds data input format (dif) block diagram 16 16 001aan39 2 lvds receiver to dac a to dac b pa[15..0] pb[15..0] 16 16 i[15..0] q[15..0] lclk ld[15]p ld[15]n ld[0]p ld[0]n lclkp lclkn data format
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 16 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.4.2 input port mapping inverting the order of the lsb and the msb of the lvds bus using bit word_swap in register ld_cntrl (see ta b l e 8 8 ) also simplifies the design of the pcb (see ta b l e 9 ). 10.4.3 input port swapping the lvds ddr receiver block internally ma ps the incoming lvds data bus into two buses with a single data rate ( figure 7 ). these two buses can be swapped internally using bit ldab_swap of register ld_cntrl (see table 88 and figure 8 ). table 9. input lvds bus swapping internal lvds bus external lvds bus (word_swap = 0) external lvds bus (word_swap = 1) ldi[15]p,n ld[15]p,n ld[0]p,n ldi[14]p,n ld[14]p,n ld[1]p,n ldi[13]p,n ld[13]p,n ld[2]p,n ldi[12]p,n ld[12]p,n ld[3]p,n ldi[11]p,n ld[11]p,n ld[4]p,n ldi[10]p,n ld[10]p,n ld[5]p,n ldi[9]p,n ld[9]p,n ld[6]p,n ldi[8]p,n ld[8]p,n ld[7]p,n ldi[7]p,n ld[7]p,n ld[8]p,n ldi[6]p,n ld[6]p,n ld[9]p,n ldi[5]p,n ld[5]p,n ld[10]p,n ldi[4]p,n ld[4]p,n ld[11]p,n ldi[3]p,n ld[3]p,n ld[12]p,n ldi[2]p,n ld[2]p,n ld[13]p,n ldi[1]p,n ld[1]p,n ld[14]p,n ldi[0]p,n ld[0]p,n ld[15]p,n fig 7. lvds ddr receiver mapping ldab swap = 0 001aan39 3 a0 b0 a1 b1 a2 b2 a3 b3 lvds receiver ld[15..0]p/n lclkp/n pa[15..0] pb[15..0] lclk a0 a1 to dac a to dac b a2 a3 b0 b1 b2 b3
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 17 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.4.4 input port formatting the lvds ddr input bus multiplexes two 16 -bit streams. the lvds receiver block demultiplexes these two streams. the two streams can carry two data formats: ? folded ? interleaved the data format block is in charge of the data format adaptation (see figure 9 ). the DAC1627D1G25 can correctly decode th e input stream using bit iq_format of register ld_cntrl (see ta b l e 8 8 ), because it can determine which format is used on the lvds ddr bus. ta b l e 1 0 shows the format mapping between the lvds input data and the data sent to the two dac channels depending on the data format selected. fig 8. lvds ddr receiver mapping ldab swap = 1 001aan39 4 a0 b0 a1 b1 a2 b2 a3 b3 lvds receiver ld[15..0]p/n lclkp/n pa[15..0] pb[15..0] lclk b0 b1 to dac a to dac b b2 b3 a0 a1 a2 a3 fig 9. lvds ddr data formats 001aan39 5 a0 b0 a1 b1 a2 b2 a3 b3 lvds receiver ld[15..0]p/n lclkp/n pa[15..0] pb[15..0] lclk data format a0 a1 a2 a3 b0 b1 b2 b3 i0 i1 to dac a to dac b i2 i3 q0 q1 q2 q3 table 10. folded and interleaved format mapping data format data bit mapping interleaved format (iq_format = 1) in[15. .0] = an[15..0]; qn [15..0] = bn[15..0] folded format (iq_format = 0) in[15..8 ] = an[15..8]; in [7..0] = bn[15..8] qn[15..8] = an[7..0]; qn[7..0] = bn[7..0]
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 18 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.5 input clock the DAC1627D1G25 opera tes with two clocks, one for the lvds ddr interface and one for the dac core. 10.5.1 lvds ddr clock the lvds ddr clock can be interfaced as shown in figure 10 because the clock buffer contains a 100 internal resistor. 10.5.2 dac core clock the dac core clock can achieve a frequency of up to 1.25 gsps. it includes internal biasing to support both ac-coupling and dc-coupling. the clock can be easily connected to any lvds, cml or pecl clock sources. depending on the interface selected, the hardware configuration varies (see figure 11 to figure 13 ). fig 10. lvds ddr clock configuration 001aan811 z = 100 100 dac1627d lvds lclkp lclkn lvds a. dc-coupling b. ac-coupling fig 11. dac core clock: lvds configuration 001aan813 z = 100 100 lvds clkp clkn dac1627d 001aan812 z = 100 100 lvds clkp clkn dac1627d 100 nf 100 nf
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 19 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.6 timing the DAC1627D1G25 can operate at an update rate (f s ) of up to 1.25 gsps and with an input data rate (f data ) of up to 312.5 mhz. the sampling position of the lvds data can be tuned using a 16-step compensation delay clock. the delay clock (see figure 14 , signals ldclkpcp and ldclkncp) is used internally to obtain a control signal, which enables calibrating the compensation delay at start-up and monitoring if the sampling position is properly aligned. figure 14 shows how the compensation delay he lps to recover the lvds ddr data on both the a and b paths. fig 12. dac core clock: cml configuration with ac-coupling fig 13. dac core clock: pecl configuration with ac-coupling 001aan831 z = 50 50 dac1627d z = 50 cml 3.3 v 50 3.3 v clkp clkn 100 nf 100 nf 001aan832 z = 50 100 200 200 dac1627d z = 50 pecl clkp clkn 100 nf 100 nf
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 20 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating the compensation delay time, referred to as t cmp in figure 14 , can be tuned automatically or manually. automatic tuning is recommended for a high-speed lvds data rate (> 300 mhz). the external lvds data and clock signals alig ns the rising and falling edges. the timing requirement is defined in figure 15 and in table 5 . when tuning manually, the compensation delay time (t cmp in figure 14 ), can be tuned as shown in ta b l e 11 using bits ldclk_del[3:0] of register man_ldclkdel (see table 81 ) and bit cal_cntrl of register main_cntrl (see table 80 ). fig 14. lvds ddr demux timing (lvds a an d b paths not swapped; ldab_swap = 0) t sk(min) = minimum skew time t sk(max) = maximum skew time fig 15. timing requirem ent automatic tuning 001aan40 0 d n [i] d n [i] d n + 1 [i] d n + 1 [i] d n + 3 [i] d n ? 1 [i] t cmp d n ? 1 [i] d n + 2 [i] d n + 2 [i] ldclkn ldclkp ld[i]n ld[i]p ldclkncp ldclkpcp lda[i] ldb[i] 001aan833 lvds data lvds clock v ih v il v ih v il t sk(min) t sk(max)
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 21 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.7 operating modes the DAC1627D1G25 requires two differential clocks: ? the lvds clock (ldclkp, ldclkn) for the lvds ddr interface ? the data clock (clkp, clkn) for the internal pll and the dual dac core the clock domain interface (cdi) and the pll have to be set correctly to configure the DAC1627D1G25 for an application mode . the default application is a 2 upsampling mode (see section 10.7.1 ). the cdi can also support 4 and 8 upsampling modes (see section 10.7.2 and section 10.7.3 ). table 11. compensation delay values for manual tuning ldclk_del[3:0] cal_cntrl typical compensation delay time xxx 0 t cmp controlled by dcsmu block (automatic control) 0000 1 360 ps to 405 ps 0001 1 435 ps to 540 ps 0010 1 525 ps to 645 ps 0011 1 600 ps to 720 ps 0100 1 690 ps to 825 ps 0101 1 780 ps to 900 ps 0110 1 885 ps to 1035 ps 0111 1 960 ps to 1200 ps 1000 1 1260 ps to 1980 ps 1001 1 1350 ps to 2160 ps 1010 1 1440 ps to 2340 ps 1011 1 1512 ps to 2556 ps 1100 1 1566 ps to 2754 ps 1101 1 1620 ps to 2952 ps 1110 1 1674 ps to 3060 ps 1111 1 1710 ps to 3186 ps
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 22 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.7.1 cdi mode 0 (x2 interpolation) cdi mode 0 ( 2 interpolation) is requir ed when the value of the lvds ddr clock is twice the internal maximum cdi frequency. ta b l e 1 2 shows examples of applications using an internal pll or an external clock for the dac core. [1] bits cdi_mode[1:0] of register misc_cntrl (see table 89 ). [2] bits interpolation[1:0] of register txcfg (see table 25 ). [3] if a single sideband modulator (ssbm) is used, see bi ts nco_on and modulation[2:0] of register txcfg (see table 25 ). [4] pins clkp and clkn (see figure 2 ). [5] bit pll_pd of register pllcfg (see table 26 ). [6] bits pll_div[1:0] of register pllcfg (see table 26 ). 10.7.2 cdi mode 1 (x4 interpolation) cdi mode 1 ( 4 interpolation) is required when the values of the lvds ddr clock and the internal cdi frequency are equal. ta b l e 1 3 shows examples of applications using an internal pll or an external clock for the dac core. [1] bits cdi_mode[1:0] of register misc_cntrl (see table 89 ). [2] bits interpolation[1:0] of register txcfg (see table 25 ). [3] if ssbm is used, see bits nco_on and mo dulation[2:0] of r egister txcfg (see table 25 ). [4] pins clkp and clkn (see figure 2 ). [5] bit pll_pd of register pllcfg (see table 26 ). [6] bits pll_div[1:0] of register pllcfg (see table 26 ). table 12. cdi mode 0: operating modes examples lvds ddr rate (mhz) i rate; q rate (msps) cdi mode [1] fir mode [2] ssbm rate [3] (msps) dac rate (msps) pll configuration dac input clock [4] (mhz) pll status [5] pll divider [6] 320 320 0 2 640 640 320 enabled 2 320 320 0 2 640 640 640 disabled n.a. table 13. cdi mode 1: operating modes examples lvds ddr rate (mhz) i rate; q rate (msps) cdi mode [1] fir mode [2] ssbm rate [3] (msps) dac rate (msps) pll configuration dac input clock [4] (mhz) pll status [5] pll divider [6] 250 250 1 4 1000 1000 250 enabled 4 250 250 1 4 1000 1000 1000 disabled n.a.
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 23 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.7.3 cdi mode 2 (x8 interpolation) cdi mode 2 ( 8 interpolation) is required when the lvds ddr clock is half the maximum cdi frequency or less. table 14 shows examples of applications using an internal pll or an external clock for the dac core. [1] bits cdi_mode[1:0] of register misc_cntrl (see table 89 ). [2] bits interpolation[1:0] of register txcfg (see table 25 ). [3] if ssbm is used, see bits nco_on and mo dulation[2:0] of r egister txcfg (see table 25 ). [4] pins clkp and clkn (see figure 2 ). [5] bit pll_pd of register pllcfg (see table 26 ). [6] bits pll_div[1:0] of register pllcfg (see table 26 ). 10.8 fir filters the DAC1627D1G25 integrates three selectable finite impulse response (fir) filters which enable the use of the device with 2, 4 or 8 interpolation rates. all three interpolation fir filters have a stop-band attenuation of at least 80 dbc and a pass-band ripple of less than 0.0005 db. ta b l e 1 5 shows the coefficients of the interpolation filters. table 14. cdi mode 2: operating modes examples lvds ddr rate (mhz) i rate; q rate (msps) cdi mode [1] fir mode [2] ssbm rate [3] (msps) dac rate (msps) pll configuration dac input clock [4] (mhz) pll status [5] pll divider [6] 125 125 2 8 1000 1000 125 enabled 4 125 125 2 8 1000 1000 1000 disabled n.a. fig 16. first stage half-band filter response nf (fs) 0 0.5 0.4 0.2 0.3 0.1 001aao039 magnitude (db) 0 -100 -20 -40 -80 -60
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 24 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating fig 17. second stage half-band filter response fig 18. third stage half-band filter response table 15: interpolation filter coefficients first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value h(14) - 65536 h(6) - 32768 h(4) - 1024 h(13) h(15) 41501 h(5) h(7) 20272 h(3) h(5) 615 h(12) h(16) ? 13258 h(4) h(8) ? 5358 h(2) h(6) ? 127 h(11) h(17) 7302 h(3) h(9) 1986 h(1) h(7) 27 h(10) h(18) ? 4580 h(2) h(10) ? 654 h(0) h(8) ? 3 h(9) h(19) 2987 h(1) h(11) 159 - - - h(8) h(20) ? 1951 h(0) h(12) ? 21 - - - h(7) h(21) 1250 - - - - - - nf (fs) 0 0.5 0.4 0.2 0.3 0.1 001aao040 magnitude (db) 0 -100 -20 -40 -80 -60 nf (fs) 0 0.5 0.4 0.2 0.3 0.1 001aao041 magnitude (db) 0 -100 -20 -40 -80 -60
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 25 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.9 single sideband modulator (ssbm) the ssbm is a quadrature modulator that enables mixing the i data and q data with the sine and cosine signals generated by the nco to generate path a and path b (see figure 19 ). the frequency of the nco is programmed over 40 bits. nco enables inverting the sine component to operate a positive or ne gative, lower or upper ssb upconversion (see register txcfg in ta b l e 2 5 ). 10.9.1 nco in 40 bits when using nco, the frequency can be set over 40 bits by five registers, freqnco_b0 to freqnco_b4 (see table 27 to table 31 ). the frequency is calculated with equation 1 . (1) h(6) h(22) ? 773------ h(5) h(23) 456 - - - - - - h(4) h(24) ? 252------ h(3) h(25) 128 - - - - - - h(2) h(26) ? 58------ h(1)h(27)22------ h(0) h(28) ? 6------ table 15: interpolation filter coefficients ?continued first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value fig 19. ssbm principle 001aan57 5 +/ ? cos a b i sin +/ ? sin q cos +/ ? f nco mf s 2 40 -------------- =
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 26 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating where: ? m is the two?s complement coding representation of freq_nco[40:0] ? f s is the dac clock sampling frequency the default settings are: ? f nco =96mhz ? f s =640msps the phase of the nco can be set by r egisters phinco_lsb an d phinco_msb over 16 bits from 0 to 360 (see ta b l e 4 4 and ta b l e 4 5 ). 10.9.2 nco low power when using nco low power (bit nco_lp_sel; see ta b l e 2 5 ), the frequency can be set by the five msb-bits of register freqnco_b4 (bits freq_nco[39:35]; see ta b l e 3 1 ). the frequency is calculated with equation 2 . (2) where: ? m is the two?s complement coding representation of freq_nco[39:35] ? f s is the dac clock sampling frequency the phase of the nco low power can be se t by the five msb-bits of register phinco_msb (see ta b l e 4 5 ). 10.9.3 complex modulator the complex modulator upconverts the single side band by mixing nco signals and i and q input signals. ta b l e 1 6 shows the various possibilities se t by bits modulation[2:0] of register txcfg (see ta b l e 2 5 ). f nco mf s 2 5 -------------- = table 16. complex modulator operation mode modulation[2:0] mode path a path b 000 bypass 001 positive upper ssb 010 positive lower ssb 011 negative upper ssb 100 negative lower ssb others not defined - - it () qt () it () nco t () cos q t () nco t () sin ? it () nco t () sin q t () nco t () cos + it () nco t () cos q t () nco t () sin + it () nco t () sin q t () nco t () cos ? it () nco t () cos q t () nco t () sin ? it () ? nco t () sin q t () nco t () cos ? it () nco t () cos q t () nco t () sin + it () ? nco t () sin q t () nco t () cos +
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 27 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.9.4 minus 3db in normal use, a full-scale pattern is also fu ll-scale at the dac out put. nevertheless, when the i data and q data come close to full-scale simultaneously, some clipping can occur. the minus 3db function (bit minus_ 3db of register dac_out_ctrl; see table 38 ) can be used to reduce the 3 db gain in the modulator. it retains a full-scale range at the dac output without added interferers. 10.10 inverse sinx / x a selectable fir filter is incorporated to compensate the sinx / x effect caused by the roll-off effect of the dac. this filter introduces a loss of 3. 4 db at dc. the coefficients are represented in ta b l e 1 7 . 10.11 dac transfer function the full-scale output current for each dac is the sum of the two complementary current outputs: ? ? the output current of dac a depends on the di gital input data and the gain factor defined by bits dac_a_dgain[7:0] of register dac_a_dgain_lsb (see ta b l e 3 4 ) and bits dac_a_dgain[11:8] of regi ster dac_a_dgain_msb (see ta b l e 3 5 ). (3) (4) the output current of dac b depends on the di gital input data and the gain factor defined by bits dac_b_dgain[7:0] of register dac_b_dgain_lsb (see ta b l e 3 6 ) and bits dac_b_dgain[11:8] of regi ster dac_b_dgain_msb (see ta b l e 3 7 ). (5) (6) table 17. inversion filter coefficients first interpolation filter lower upper value h(1) h(9) +1 h(2) h(8) ? 4 h(3) h(7) +13 h(4) h(6) ? 51 h(5) - +610 i oa fs () i ioutap i ioutan + = i ob fs ) () i ioutbp i ioutbn + = i ioutap i oa fs () dacadgain () 1024 ----------------------------------------- data 65535 () () ------------------------ ?? ?? = i ioutan i oa fs () 1 dacadgain () 1024 ----------------------------------------- data 65535 () () ------------------------ ?? ?? ? ?? ?? = i ioutbp i ob fs () dacbdgain () 1024 ----------------------------------------- data 65535 () () ------------------------ ? ? ? ? = i ioutbn i ob fs () 1 dacbdgain () 1024 ----------------------------------------- data 65535 () () ------------------------ ?? ?? ? ?? ?? =
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 28 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating it is possible to define if the dac1627d1g 25 operates with a binary input or a two's complement input (bit coding; see ta b l e 2 4 ). ta b l e 1 8 shows the output current as a function of the input data, when i oa(fs) =i ob(fs) =20ma. 10.12 full-scale current 10.12.1 regulation the DAC1627D1G25 reference circuitry integrat es an internal band gap reference voltage which delivers a 1.25 v reference on the gapout pin. it is recommended to decouple pin gapout using a 100 nf capacitor. the reference current is generated via an external resistor of 910 (1 %) connected to vires and a control amplifier sets the appropriate full-scale current (i oa(fs) and i ob(fs) ) for both dacs (see figure 20 )). figure 20 shows the optimal configuration for te mperature drift compensation because the band gap reference voltage can be matched to the voltage across the feedback resistor. the dac current can also be adjusted by applying an external reference voltage to the non-inverting input pin gapout and by disabling the internal band gap reference voltage (bit gap_pon of the common register; see ta b l e 2 4 ). 10.12.2 full-scale current adjustment the default full-scale current (i o(fs) ) is 20 ma but further adjustments can be made by the user to both dacs independently via the serial interface from 6.95 ma to 28.7 ma, 11 %. table 18. dac transfer function data i15 to i0/q15 to q0 (binary coding) i15 to i0/q15 to q0 (two?s complement coding ioutap/ioutbp ioutan/ioutbn 0 0000 0000 0000 0000 1000 0000 0000 0000 0 ma 20 ma ... ... ... ... .... 32768 1000 0000 0000 0000 0000 0000 0000 0000 10 ma 10 ma ... ... ... ... ... 65535 1111 1111 1111 1111 0111 1111 1111 1111 20 ma 0 ma fig 20. internal reference configuration 001aan834 910 (1 %) 100 nf dac current sources array band gap reference gapout a gnd a gnd vires dac1627d
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 29 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating the settings applied to dac_a_gain_coarse[3:0] (register 17h; see ta b l e 4 6 and register 18h see ta b l e 4 7 ;) and to dac_b_gain coarse[3:0] (register 19h; see ta b l e 4 8 and register 1ah see ta b l e 4 9 ;) define the coarse variation of the full-scale current (see ta b l e 1 9 ). the settings applied to dac_a_gain_fine[5:0] (see register 17h in table 46 ) and to dac_b_gain_fine[5:0] (see register 19h in ta b l e 4 8 ) define the fine variation of the full-scale current (see ta b l e 2 0 ). 10.13 digital offset adjustment the DAC1627D1G25 provides digital offset correction (bits dac_a_offset[7:0] in ta b l e 4 0 and bits dac_a_offset[15:8] in ta b l e 4 1 and register dac_b_offset[7:0] in ta b l e 4 2 and bits dac_b_offset[15:8] in ta b l e 4 3 ) which can be used to adjust the common-mode level at the output of each dac. it adds an offset at the end of the digital part, just before the dacs. ta b l e 2 1 shows the range of variat ion of the digital offset. table 19. i o(fs) coarse adjustment default settings are shown highlighted. dac_gain_coarse[3:0] i o(fs) (ma) decimal binary 0 0000 6.95 1 0001 8.4 2 0010 9.85 3 0011 11.3 4 0100 12.75 5 0101 14.2 6011015.65 7011117.1 8 1000 18.55 9 1001 20 10 1010 21.45 11 1011 22.9 12 1100 24.35 13 1101 25.8 14 1110 27.25 15 1111 28.7 table 20. i o(fs) fine adjustment default settings are shown highlighted. dac_gain_fine[5:0] i o(fs) (%) decimal two?s complement ? 32 10 0000 ? 11 ... ... ... 00000000 ... ... ... +31 01 1111 +11
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 30 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.14 analog output the device has two output channels, producing two complementary current outputs, which enable the reduction of even-order harmonics and noise. the pins are ioutap/ioutan and ioutbp/ioutbn. they have to be connected via a load resistor r l to the 3.3 v analog power supply (v dda(3v3) ). figure 21 shows the equivalent analog output circ uit of one dac. this circuit includes a parallel combination of nmos current sources and associated switches for each segment. the cascode source configuration increases the output impedance of the source, which improves the dynamic performance of the dac because there is less distortion. depending on the application, the various stages and the targeted performances, the device can be used for an output level of up to 2 v (p-p). table 21. digital offset adjustment dac_a_offset[15:0] dac_b_offset[15:0] (two?s complement) offset applied 1000 0000 0000 0000 ? 32768 1000 0000 0000 0001 ? 32767 ... ... 1111 1111 1111 1111 ? 1 0000 0000 0000 0000 0 0000 0000 0000 0001 +1 ... ... 0111 1111 1111 1110 +32766 0111 1111 1111 1111 +32767 fig 21. equivalent analog output circuit 001aan835 r l ioutap/ioutbp ioutan/ioutbn 3.3 v gnd gnd r l 3.3 v
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 31 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.15 auxiliary dacs the DAC1627D1G25 int egrates two auxiliary dacs, which are used to compensate any offset between the dacs and the next stage in the transmission path. both auxiliary dacs have a 10-bit resolution and are current sources (referenced to ground). the full-scale output current for each dac is the sum of the two complementary current outputs: ? ? the output current depends on the digital input data set by spi registers dac_a_aux_msb (bits aux_a[9:2]; see ta b l e 5 0 ), dac_a_aux_lsb (bits aux_a[1:0]; see ta b l e 5 1 ), dac_b_aux_msb (bits aux_b[9:2]; see ta b l e 5 2 ) and dac_b_aux_lsb (bits aux_b[1:0]; see ta b l e 5 3 ). (7) (8) (9) (10) ta b l e 2 2 shows the output current as a function of the aux iliary dacs data dataa and datab above. table 22. auxiliary dac transfer function dataa; datab aux_a[9:2]/aux_a[1:0]; aux_b[9:0]/aux_b[1:0] (binary coding i auxap ; i auxbp (ma) i auxan ; i auxbn (ma) 0 00 0000 0000 0 2.2 ... ... ... ... 512 10 0000 0000 1.1 1.1 ... ... ... ... 1023 11 1111 1111 2.2 0 i oauxa fs () i auxap i auxan + = i oauxb fs () i auxbp i auxbn + = i auxap i oauxa fs () dataa 1023 ------------------- - ?? ?? = i auxan i oauxa fs () 1023 dataa ? 1023 ------------------------------------- - ?? ?? = i auxbp i oauxb fs () datab 1023 ------------------- - ?? ?? = i auxbn i oauxb fs () 1023 datab ? 1023 ------------------------------------- - ?? ?? =
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 32 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.16 output c onfiguration 10.16.1 basic output configuration the use of a differentially co upled transformer output (see figure 22 ) provides optimum distortion performance. in a ddition, it helps to match the impedance and provides electrical isolation. the DAC1627D1G25 can operate a differential output of up to 2 v (p-p). in this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor, which is connected to the 3.3 v analog power supply. this adjusts the dc common-mode to around 2.7 v (see figure 23 ). fig 22. 1 v (p-p) differential output with transformer fig 23. 2 v (p-p) differential output with transformer 001aan836 50 50 2:1 50 ioutap/ioutbp dac1627d ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.8 v v o(dif) = 1 v ioutan/ioutbn 3.3 v 3.3 v 0 ma to 20 ma 0 ma to 20 ma 001aan837 100 4:1 100 ioutap/ioutbp dac1627d ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.7 v v o(dif) = 2 v ioutan/ioutbn 3.3 v 62 50 3.3 v 3.3 v 0 ma to 20 ma 0 ma to 20 ma
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 33 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.16.2 iq-modulator - bgx7100 interface the DAC1627D1G25 can be easily connected to the bgx7100 nxp iq-modulator. the offset compensation for local oscillator can be cancelled using the digital offset control in the device. figure 24 shows an example of a connection between the DAC1627D1G25 and the bgx7100 interface. 10.16.3 iq-modulator - dc interface when the system operation requires to keep the dc component of the spectrum, the DAC1627D1G25 can use a dc interface to connect an iq-modulator. in this case, the offset compensation for local oscillator can be cancelled using the digital offset control in the device. figure 25 shows an example of a connection to an iq modulator with a 1.7 v common input level. fig 24. DAC1627D1G25 with bgx7100 iq-modulator interface ioutap/ioutbp 3.3 v dac1627d bgx7100 iq-modulator 51.1 51.1 ioutan/ioutbn auxap/auxbp auxan/auxbn bbap/bbbp bban/bbbn 001aan814 0 ma to 20 ma fig 25. iq-modulator: dc interface with a 1.7 v common input level ioutap/ioutbp 3.3 v dac1627d 51.1 442 442 51.1 768 768 ioutan/ioutbn bbap/bbbp bbap/bban bbbp/bbbn v i(cm) = 1.7 v v i(dif) = 1.26 v ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.67 v v o(dif) = 1.98 v iq-modulator (v i(cm) = 1.7 v) bban/bbbn 001aan838 0 ma to 20 ma
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 34 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating figure 26 shows an example of a connection to an iq-modulator with a 3.3 v common input level. the auxiliary dacs can be used to control the offset withi n an accurate range or with accurate steps. figure 27 shows an example of a connection to an iq-modulator with a 1.7 v common input level and auxiliary dacs. fig 26. iq-modulator: dc interface with a 3.3 v common input level fig 27. iq-modulator: dc interface with a 1. 7 v common input level and auxiliary dacs ioutap/ioutbp 3.3 v dac1627d 54.9 237 237 54.9 5 v 750 750 1.27 k 1.27 k ioutan/ioutbn bbap/bbbp bbap/bban bbbp/bbbn v i(cm) = 3.3 v v i(dif) = 1.5 v ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.75 v v o(dif) = 1.97 v iq-modulator (v i(cm) = 3.3 v) bban/bbbn 001aan839 ioutap/ioutbp 3.3 v dac1627d 51.1 442 442 51.1 51.1 51.1 698 698 ioutan/ioutbn auxap/auxbp auxan/auxbn bbap/bbbp bbap/bban bbbp/bbbn v i(cm) = 1.7 v v i(dif) = 1.23 v offset correction = up to 50 mv ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.67 v v o(dif) = 1.94 v bban/bbbn 001aan840 0 ma to 20 ma 1.1 ma (typical)
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 35 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating figure 28 shows an example of a connection to an iq-modulator with a 3.3 v common input level and auxiliary dacs. the constraints to adjust the interface are: ? the output compliance range of the dac ? the output complia nce range of the auxiliary dacs ? the input common-mode level of the iq-modulator ? the range of offset correction fig 28. iq-modulator: dc interface with a 3. 3 v common input level and auxiliary dacs ioutap/ioutbp 3.3 v dac1627d 54.9 237 237 54.9 5 v 750 750 442 442 634 634 ioutan/ioutbn auxap/auxbp auxan/auxbn bbap/bbbp bbap/bban bbbp/bbbn v i(cm) = 3.3 v v i(dif) = 1.5 v offset correction = up to 36 mv ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.75 v v o(dif) = 1.96 v bban/bbbn 001aan841
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 36 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.16.4 iq-modulator - ac interface when the iq-modulator common-mode voltage is close to ground, the DAC1627D1G25 must be used ac-coupled and the auxiliary dacs are required for local oscillator cancellation. figure 29 shows an example of a connection to an iq-modulator with a 0.5 v common input level and auxiliary dacs. 10.17 design recommendations 10.17.1 power and grounding use a separate power supply regulator for the generation of the 1.8 v analog power (pins 65, 62, 55, 69, 72 and 58) and the 1.8 v digital power (pins 12, 19, 36, 26 and 43) to ensure optimal performance. also, include individual lc decoupling fo r the following six sets of power pins: ? v dda(1v8)_p1 (pin 62) ? v dda(1v8)_p2 (pin 65) ? v dda(1v8) (pins 55, 69, 72 and 58) ? v ddd(1v8) (core: pins 12, 26 and 43) ? v ddd(1v8) (lvds: pins 19 and 36) ? v dda(3v3) (pins 59 and 68) at least two capacitors must be used for each power pin decoupling. these capacitors must be located as close as possibl e to the DAC1627D1G25 power pins. fig 29. iq-modulator: ac interface with a 0. 5 v common input level and auxiliary dacs ioutap/ioutbp 3.3 v dac1627d 65.5 65.5 5 v 2 k 2 k 34 34 174 174 ioutan/ioutbn auxap/auxbp auxan/auxbn bbap/bbbp bbap/bban bbbp/bbbn v i(cm) = 0.5 v v i(dif) = 1.96 v offset correction = up to 70 mv ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.65 v v o(dif) = 1.96 v bban/bbbn 001aan842 10 nf 10 nf 0 ma to 20 ma 1.1 ma (typical) iq-modulator (v i(cm) = 0.5 v)
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 37 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating the die pad is used for both the power dissipation and electrical grounding. insert several vias (typically 7 7) to connect the internal ground plane to the top layer die area. 10.18 configuration interface 10.18.1 register description the DAC1627D1G25 incorporates more than the 32 spi registers allowed by the address value a[4:0]. it uses three spi register pages (page_00, page_01, and page_0a), each containing 32 registers. the 32nd register of each page indicates which page is currently addressed (00h, 01h or 0ah). page 00h (see ta b l e 2 3 ) is dedicated to the main control of the DAC1627D1G25: ? mode selection ? nco control ? auxiliary dac control ? gain/phase/off set control ? power-down control page 01h (see ta b l e 5 5 ) is dedicated to: ? multi-device sync hronization (mds) ? dac analog core control (biasing current, sleep mode) page 0ah (see ta b l e 7 9 ) is dedicated to the lvds input interface configuration.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 38 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating 10.18.2 page 0 register allocation map ta b l e 2 3 shows an overview of all registers on page 0 (00h in hexadecimal). see section 10.18.3 for detailed descriptions of the registers. table 23. page_00 register allocation map address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dec 0 00h common r/w 3w_spi spi_rst - - - coding ic_pon gap_pon 1000 0111 87h 135 1 01h txcfg r/w nco_on nco_lp _sel inv_sin _sel modulation[2:0] interpolation[1:0] 0000 0001 01h 1 2 02h pllcfg r/w pll_bp pll_buf _pd pll_pll _pd pll_div[1:0] pl l_phase[1:0] pll_ osc_pd 1010 0001 a1h 161 4 04h freqnco_b0 r/w freq_nco[7:0] 0110 0110 66h 102 5 05h freqnco_b1 r/w freq_nco[15:8] 0110 0110 66h 102 6 06h freqnco_b2 r/w freq_nco[23:16] 0110 0110 66h 102 7 07h freqnco_b3 r/w freq_nco[31:24] 0010 0110 66h 102 8 08h freqnco_b4 r/w freq_nco[39:32] 0010 0110 26h 38 9 09h ph_corr_ctl0 r/w phase_cor[7:0] 0000 0000 00h 0 10 0ah ph_corr_ctl1 r/w ph_cor _ena - - phase_cor[12:8] 0000 0000 00h 0 11 0bh dac_a_dgain_lsb r/w dac_a_dgain[7:0] 1101 0100 50h 80 12 0ch dac_a_dgain_msb r/w - - - - dac_a_dgain[11:8] 0000 1011 0bh 11 13 0dh dac_b_dgain_lsb r/w dac_b_dgain[7:0] 1101 0100 50h 80 14 0eh dac_b_dgain_msb r/w - - - - dac_b_dgain[11:8] 0000 0010 0bh 11 15 0fh dac_out_ctrl r/w - - - - a_dgain_e b_dgain_e minus _3db clipping _ena 0000 0000 00h 0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 39 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating 16 10h dac_clipping r/w clipping_level[7:0] 1111 1111 ffh 255 17 11h dac_a_offset_lsb r/ w dac_a_offset[7:0] 0000 0000 00h 0 18 12h dac_a_offset_msb r/w dac_a_offset[15:8] 0000 0000 00h 0 19 13h dac_b_offset_lsb r/ w dac_b_offset[7:0] 0000 0000 00h 0 20 14h dac_b_offset_msb r/w dac_b_offset[15:8] 0000 0000 00h 0 21 15h phinco_lsb r/w ph_nco[7:0] 0000 0000 00h 0 22 16h phinco_msb r/w ph_nco[15:8] 0000 0000 00h 0 23 17h dac_a_gain1 r/w dac_a_gain_ coarse[1:0] dac_a_gain_fine[5:0] 0100 0000 40h 64 24 18h dac_a_gain2 r/w dac_a_gain_ coarse[3:2] - - - - - - 1000 0000 80h 128 25 19h dac_b_gain1 r/w dac_b_gain_ coarse[1:0] dac_b_gain_fine[5:0] 0100 0000 40h 192 26 1ah dac_b_gain2 r/w dac_b_gain_ coarse[3:2] - - - - - - 1000 0000 80h 128 27 1bh dac_a_aux_msb r/w aux_a[9:2] 1000 0000 80h 128 28 1ch dac_a_aux_lsb r/w aux_a _pd - - - - - aux_a[1:0] 0000 0000 00h 0 29 1dh dac_b_aux_msb r/w aux_b[9:2] 1000 0000 80h 128 30 1eh dac_b_aux_lsb r/w aux_b _pd - - - - - aux_b[1:0] 0000 0000 00h 0 31 1fh page_address r/w - - - - - page_add[2:0] 0000 0000 00h 0 table 23. page_00 register allocation map ?continued address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dec
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 40 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.18.3 page 0 bit definition detailed description table 24. register common (address 00h) bit description default values are shown highlighted. bit symbol access value description 7 3w_spi r/w serial interface bus type 0 4-wire spi 1 3-wire spi 6 spi_rst r/w serial interface reset 0 no reset 1 performs a reset on all registers except address 00h 2 coding r/w coding of input word 0 two complement?s coding 1 unsigned format 1 ic_pon r/w ic power control 0 all circuits (digital and analog, except spi) are in power-down 1 all circuits (digital and analog, except spi) are switched on 0 gap_pon r/w internal band gap power control 0 band gap is power-down 1 internal band gap references are switched on table 25. register txcfg (address 01h) bit description default values are shown highlighted. bit symbol access value description 7 nco_on r/w nco 0 nco disabled, the nco phase is reset to 0 1 nco enabled 6 nco_lp_sel r/w nco low power selection 0 low power nco disabled 1 low power nco enabled (frequency and phase given by the five msb of the registers 06h and 08h, respectively) 5 inv_sin_sel r/w inverse (sin x) / x function selection 0 disable 1 enable 4 to 2 modulation[2:0] r/w modulation 000 dual dac: no modulation 001 positive upper single sideband upconversion 010 positive lower single sideband upconversion 011 negative upper single sideband upconversion 100 negative lower single sideband upconversion others not defined
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 41 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 1 to 0 interpolation[1:0] r/w interpolation 00 no interpolation 01 2 interpolation 10 4 interpolation 11 8 interpolation table 25. register txcfg (address 01h) bit description ?continued default values are shown highlighted. bit symbol access value description table 26. register pllcfg (address 02h) bit description default values are shown highlighted. bit symbol access value description 7 pll_bp r/w pll bypass 0 dac clock generated by pll 1 dac clock provided via external pins clkn and clkp (pll bypass mode) 6 pll_buf_pd r/w pll test buffer control 0 power-down mode 1 enabled 5 pll_pll_pd r/w pll and ckgen control 0 power-down mode 1 enable 4 to 3 pll_div[1:0] r/w pll divider factor 00 f s =2 f data 01 f s =4 f data 10 f s =8 f 11 undefined 2 to 1 pll_phase[1:0] r/w pll phase shift 00 0 degrees phase shift of f s 01 120 degrees phase shift of f s 10 240 degrees phase shift of f s 11 240 degrees phase shift of f s 0 pll_osc_pd r/w pll oscillator output power-down 0 power-down mode 1 enabled table 27. register freqnco_b0 (address 04h) default values are shown highlighted. bit symbol access value description 7 to 0 freq_nco[7:0] r/w nco freque ncy (two complement?s coding) - least significant 8 bits for the nco frequency setting
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 42 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 28. register freqnco_b1 (address 05h) default values are shown highlighted. bit symbol access value description 7 to 0 freq_nco[15:8] r/w nco frequency - intermediate 8 bits for the nco frequency setting table 29. register freqnco_b2 (address 06h) default values are shown highlighted. bit symbol access value description 7 to 0 freq_nco[23:16] r/w nco frequency - intermediate 8 bits for the nco frequency setting table 30. register freqnco_b3 (address 07h) default values are shown highlighted. bit symbol access value description 7 to 0 freq_nco[31:24] r/w nco frequency - intermediate 8 bits for the nco frequency setting table 31. register freqnco_b4 (address 08h) default values are shown highlighted. bit symbol access value description 7 to 0 freq_nco[39:32] r/w nco frequency (msb) - most significant 8 bits for the nco frequency setting table 32. register ph_corr_ctl0 (address 09h) default values are shown highlighted. bit symbol access value description 7 to 0 phase_cor[7:0]] r /w dac output phase correction factor (lsb) - least significant 8 bits for the dac output phase correction factor table 33. register ph_corr_ctl1 (address 0ah) default values are shown highlighted. bit symbol access value description 7 ph_cor_ena r/w dac output phase correction control 0 dac output phase correction disabled 1 dac output phase correction enabled 4 to 0 phase_cor[12:8] r /w dac output phase correction factor msb 00000 most significant 5 bits for the dac output phase correction factor table 34. register dac_a_dgain_lsb (address 0bh) default values are shown highlighted. bit symbol access value description 7 to 0 dac_a_dgain[7:0] r/w dac a digital gain control - least significant 8 bits for the dac a digital gain
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 43 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 35. register dac_a_dgain_msb (address 0ch) default values are shown highlighted. bit symbol access value description 3 to 0 dac_a_dgain[11:8] r/w dac a digital gain control - most significant 4 bits for the dac a digital gain table 36. register dac_b_dgain_lsb (address 0dh) default values are shown highlighted. bit symbol access value description 7 to 0 dac_b_dgain[7:0] r/w dac b digital gain control - least significant 8 bits for the dac b digital gain table 37. register dac_b_dgain_msb (address 0eh) default values are shown highlighted. bit symbol access value description 3 to 0 dac_b_dgain[11:8] r/w dac b digital gain control - most significant 4 bits for the dac b digital gain table 38. register dac_out_ctrl (address 0fh) default values are shown highlighted. bit symbol access value description 3 a_dgain_e r/w dac a digital gain control 0 disable 1 enable 2 b_dgain_e r/w dac b digital gain control 0 disable 1 enable 1 minus_3db r/w dac attenuation control 0 unity gain 1 ? 3 db gain 0 clipping_ena r/w digital dac output clipping control 0 disable 1 enable table 39. register dac_clipping (address 10h) default values are shown highlighted. bit symbol access value description 7 to 0 clipping_level[7:0] r/w - digital dac output clipping level value table 40. register dac_a_offset_lsb (address 11h) default values are shown highlighted. bit symbol access value description 7 to 0 dac_a_offset[7:0] r/w dac a digital offset value - least significant 8 bits for the dac a digital offset
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 44 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 41. register dac_a_offset_msb (address 12h) default values are shown highlighted. bit symbol access value description 7 to 0 dac_a_offset[15:8] r/w dac a digital offset value - most significant 8 bits for the dac a digital offset table 42. register dac_b_offset_lsb (address 13h) default values are shown highlighted. bit symbol access value description 7 to 0 dac_b_offset[7:0] r/w dac b digital offset value - least significant 8 bits for the dac b digital offset table 43. register dac_b_offset_msb (address 14h) default values are shown highlighted. bit symbol access value description 7 to 0 dac_b_offset[15:8] r/w dac b digital offset value - most significant 8 bits for the dac b digital offset table 44. register phinco_lsb (address 15h) default values are shown highlighted. bit symbol access value description 7 to 0 ph_nco[7:0] r/w nco phase offset lsb - least significant 8 bits for the nco phase setting table 45. register phinco_msb (address 16h) default values are shown highlighted. bit symbol access value description 7 to 0 ph_nco[15:8] r/w nco phase offset msb - most significant 8 bits for the nco phase setting table 46. register dac_a_gain1 (address 17h) default values are shown highlighted. bit symbol access value description 7 to 6 dac_a_gain_coarse[1:0] r/w - dac a analog coarse gain control (lsb) 5 to 0 dac_a_gain_fine[5:0] r/w - dac a analog fine gain control table 47. register dac_a_gain2 (address 18h) default values are shown highlighted. bit symbol access value description 7 to 6 dac_a_gain_coarse[3:2] r/w dac a analog gain coarse control (msb) table 48. register dac_b_gain1 (address 19h) default values are shown highlighted. bit symbol access value description 7 to 6 dac_b_gain_coarse[1:0] r/w - dac b analog coarse gain control (lsb) 5 to 0 dac_b_gain_fine[5:0] r/w - d ac b analog fine gain control
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 45 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 49. register dac_b_gain2 (address 1ah) default values are shown highlighted. bit symbol access value description 7 to 6 dac_b_gain_coarse[3:2] r/w - dac b analog coarse gain control (msb) table 50. dac_a_aux_msb register (address 1bh) bit description default values are shown highlighted. bit symbol access value description 7 to 0 aux_a[9:2] r/w - most signifi cant 8 bits for auxiliary dac a table 51. dac_a_aux_lsb register (address 1ch) bit description default values are shown highlighted. bit symbol access value description 7 aux_a_pd r/w auxiliary dac a power 0on 1off 1 to 0 aux_a[1:0] r/w - least significant 2 bits for auxiliary dac a table 52. dac_b_aux_msb register (address 1dh) bit description default values are shown highlighted. bit symbol access value description 7 to 0 aux_b[9:2] r/w - most significant 8 bits for auxiliary dac b table 53. dac_b_aux_lsb register (address 1eh) bit description default values are shown highlighted. bit symbol access value description 7 aux_b_pd r/w auxiliary dac b power 0on 1off 1 to 0 aux_b[1:0] r/w - least significant 2 bits for auxiliary dac b table 54. spi_page register (a ddress 1fh) bit description default values are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w - spi page address
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 46 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating 10.18.4 page 1 allocation map ta b l e 5 5 shows an overview of all registers on page 1 (01h in hexadecimal). see section 10.18.5 for detailed descriptions of the registers. table 55. page 1 register allocation map address register name r/w bit definition default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex 0 00h mds_main r/w mds_eqcheck[1:0] mds_ run mds_ nco mds_ nco_ pulse mds_ sref_ dis mds_ master mds_ ena 0000 0100 04h 1 01h mds_win_period_a r/w md s_win_period_a[7:0] 1000 0000 80h 2 02h mds_win_period_b r/w md s_win_period_b[7:0] 0100 0000 40h 3 03h mds_misccntrl0 r/w - - - mds_ eval_ ena mds_ prerun_e mds_pulsewidth[2:0] 0001 0000 10h 4 04h mds_man_adjustdly r/w mds_ man mds_man_adjustdly[6:0] 0100 0000 40h 5 05h mds_auto_cycles r/w mds_auto_cycles[7:0] 1000 0000 80h 6 06h mds_misccntrl1 r/w mds_sr_ cken mds_sr_ lockout mds_ sr_lock mds_ relock mds_lock_delay[3:0] 0000 1111 0fh 7 07h mds_offset_dly rw - - - m ds_offset_dly[4:0] 0000 0000 00h 8 08h mds_adjdelay rw - mds_adjdelay[6:0] 0000 0000 00h 9 09h mds_status0 r early late equal mds_eq early_ error late_ error equal_ found mds_ active uuuu uuuu uuh 10 0ah mds_status1 r - - add_err mds_en_phase[1:0] mds_ prerun mds_ lockout mds_ lock uuuu uuuu uuh 14 0eh dac_current_aux r/w - - - - dac_aux_bias[3:0] 0000 0011 03h 15 0fh dac_current_0 r/w - - - - dac_dig_bias[3:0] 0000 0011 03h 16 10h dac_current_1 r/w - - - - dac_mst_bias[3:0] 0000 0011 03h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 47 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating [1] u = undefined at power-up or after reset. 17 11h dac_current_2 r/w - - - - dac_drv_bias[3:0] 0000 0011 03h 18 12h dac_current_3 r/w - - - - dac_slv_bias[3:0] 0000 0011 03h 19 13h dac_current_4 r/w - - - - dac_ck_bias[3:0] 0000 0011 03h 20 14h dac_current_5 r/w - - - - dac_cas_bias[3:0] 0000 0011 03h 21 15h dac_current_6 r/w - - - - dac_bld_bias[3:0] 0000 0011 03h 22 16h dac_pon_sleep r/w dac_b_ pon dac_b_ sleep dac_b_ com_pd dac_b_ bleed_ pd dac_a_ pd dac_a_ sleep dac_a_ com_pd dac_a_ bleed_ pd 1011 1011 bbh 23 17h dac_clkdig_delay r/w - - - - - pll_dig_delay[2:0] 0000 0010 02h 31 1fh page_address r/w - - - - - page[2:0] 0000 0000 00h table 55. page 1 register allocation map ?continued address register name r/w bit definition default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 48 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.18.5 page 1 bit definition detailed description table 56. mds_main register (address 00h) bit description default values are shown highlighted. bit symbol access value description 7 to 6 mds_eqcheck[1:0] r/w lock mode 00 lock when (early = 1 and late = 1) 01 lock when (early = 1, late = 1 and equal = 1) 10 lock when equal = 1 11 force lock (equal-check = 1) 5 mds_run r/w evaluation process restart control 0 no action 1(0 1) transition restarts evaluation_counter 4 mds_nco r/w nco synchronization 0 no action 1 enable 3 mds_nco_pulse r/w nco pulse 0 no action 1 manual control nco tuning 2 mds_sref_dis r/w internal pulse generation 0 normal mode 1 disable 1 mds_master r/w mds mode selection 0 slave mode 1 master mode 0 mds_ena r/w mds function control 0 disable 1 enable table 57. mds_win_period_a register (address 01h) bit description default values are shown highlighted. bit symbol access value description 7 to 0 mds_win_period_a[7:0] r/w - determines mds window low time table 58. mds_win_period_b register (address 02h) bit description default values are shown highlighted. bit symbol access value description 7 to 0 mds_win_period_b[7:0] r/w - d etermines mds window high time table 59. mds_misccntrl0 register (address 03h) bit description default values are shown highlighted. bit symbol access value description 4 mds_eval_ena r/w mds evaluation 0 disable 1 enable
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 49 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 3 mds_prerun_ena r/w automatic mds start-up 0 no mds_win/mds_ref generation in advance 1 mds_win/mds_ref run-in before mds_evaluation 2 to 0 mds_pulsewidth[2:0] r/w width of mds (in output clk-periods) 000 1 dac clk-period 001 2 dac clk-periods 010 to 111 (mds_pulsewidth ? 1) 4 dac clk-periods table 59. mds_misccntrl0 register (address 03h) bit description ?continued default values are shown highlighted. bit symbol access value description table 60. mds_man_adjustdly register (address 04h) bit description default values are shown highlighted. bit symbol access value description 7 mds_man r/w adjustment delays mode 0 auto-control adjustment delays 1 manual control adjustment delays 6 to 0 mds_man_adjustdly[6:0 ] r/w adjustment delay value - if mds_man = 0 then initial value adjustment delay - if mds_man = 1 then controls adjustment delay table 61. mds_auto_cycles register (address 05h) bit description default values are shown highlighted. bit symbol access value description 7 to 0 mds_auto_cycles[7:0] r/w - number of ev aluation cycles applied fo r mds. if set to 255 then ic continuously generates/monitors the mds pulse table 62. mds_misccntrl1 register (address 06h) bit description default values are shown highlighted. bit symbol access value description 7 mds_sr_cken r/w - lock mode 0 free-running mds_sr_cken 1 mds_sr_cken forced low 6 mds_sr_lockout r/w lockout detector soft reset 0 mds_sr_lockout in use 1 mds_sr_lockout forced low 5 mds_sr_lock r/w lock detector soft reset 0 mds_sr_lock in use 1 mds_sr_lock forced low 4 mds_relock r/w relock mode 0 no action 1 relock when lockout occurs 3 to 0 mds_lock_delay[3:0] r/w - number of succeeding 'equal'-detections until lock
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 50 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 63. mds_offset_dly register (address 07h) bit description default values are shown highlighted. bit symbol access value description 4 to 0 mds_offset_dly[6:0] r/w - delay of fset for dataflow (two?s complement [ ? 16 to 15] table 64. mds_adjdelay register (address 08h) bit description default values are shown highlighted. bit symbol access value description 6 to 0 mds_adjdelay[6:0] r - actual value adjustment delay table 65. mds_status0 register (address 09h) bit description default values are shown highlighted. bit symbol access value description 7 early r early signal (sampled) from early-to-late detector 0false 1true 6 late r late signal (sampled) from early-to-late detector 0false 1true 5 equal r equal signal (sampled) from early-to-late detector 0false 1true 4 mds_lock r result equal-check 0false 1true 3 early_error r adjustment delay maximum value stops the search 0false 1true 2 late_error r adjustment delay minimum value stops the search 0false 1true 1 equal_found r evaluation logic has detected equal condition 0false 1true 0 mds_active r evaluation logic active 0false 1true table 66. mds_status1 register (address 0ah) bit description default values are shown highlighted. bit symbol access value description 5 add_err r adjustment del ay error detection 0ok 1 delay offset cannot be applied in available range
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 51 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 4 to 3 mds_en_phase[1:0] r mds enable phase 00 enable phase = 0 01 enable phase = 1 (only for 2) 10 enable phase = 2 (only for 2 and 4) 11 enable phase = 3 (only for 2) 2 mds_prerun r mds-prerun phase active flag 0false 1true 1 mds_lockout r mds_lockout detected flag 0false 1true 0 mds_lock r mds_lock flag 0false 1true table 66. mds_status1 register (address 0ah) bit description ?continued default values are shown highlighted. bit symbol access value description table 67. dac_current_aux register (address 0eh) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_aux_bias[3:0] r/w - bias current control (see table 75 ) table 68. dac_current_0 register (address 0fh) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_dig_bias[3:0] r/w - bias current control (see table 75 ) table 69. dac_current_1 register (address 10h) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_mst_bias[3:0] r/w - bias current control (see table 75 ) table 70. dac_current_2 register (address 11h) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_drv_bias[3:0] r/w - bias current control (see table 75 ) table 71. dac_current_3 register (address 12h) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_slv_bias[3:0] r/w - bias current control (see table 75 )
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 52 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 72. dac_current_4 register (address 13h) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_ck_bias[3:0] r/w - bias current control (see table 75 ) table 73. dac_current_5 register (address 14h) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_cas_bias[3:0] r/w - bias current control (see table 75 ) table 74. dac_current_6 register (address 15h) bit description default values are shown highlighted. bit symbol access value description 3 to 0 dac_bld_bias[3:0] r/w - bias current control (see table 75 ) table 75. bias current control table bias[3:0] deviation from nominal current 0 0 0 ? 30 % 0 0 1 ? 20 % 0 1 0 ? 10 % 0 1 1 0 % 1 0 0 +10 % 1 0 1 +20 % 1 1 0 +30 % 1 1 1 +40 % table 76. dac_pon_sleep register (address 16h) bit description default values are shown highlighted. bit symbol access value description 7 dac_b_pon r/w - dac b power control 0 power-down 1 power on 6 dac_b_sleep r dac b mode selection 0 normal operation 1 sleep mode 5 dac_b_com_pd r commutator b control 0 disable (power-down) 1 enable 4 dac_b_bleed_pd r dac b bleed current control 0 disable (power-down) 1 enable 3 dac_a_pon r dac a power control 0 power-down 1 power on
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 53 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 2 dac_a_sleep r dac b mode selection 0 normal operation 1 sleep mode 1 dac_a_com_pd r commutator a control 0 disable (power-down) 1 enable 0 dac_a_bleed_pd r dac a bleed current control 0 disable (power-down) 1 enable table 76. dac_pon_sleep register (address 16h) bit description ?continued default values are shown highlighted. bit symbol access value description table 77. dac_test_8 register (a ddress 17h) bit description default values are shown highlighted. bit symbol access value description 2 to 0 pll_dig_delay[2:0] r/w - digital cl ock delay offset of pll/ckgen_div8 table 78. spi_page register (a ddress 1fh) bit description default values are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w - spi page address
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 54 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating 10.18.6 page a register allocation map ta b l e 7 9 shows an overview of all registers on page a (0ah in hexadecimal). see section 10.18.7 for detailed descriptions of the registers. table 79. page_0a register allocation map address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dec 0 00h main_cntrl r/w - - - ld_pd pd_cntrl cal_ cntrl rst_ dckl rst_ lckl 0000 0011 03h 3 1 01h man_ldclkdel r/w - - - - ldclk_del[3:0] 0000 0000 00h 0 2 02h dbg_lvds r/w - - - - sber reserved 0000 0000 00h 0 4 04h rst_ext_ldclk r/w rst_ext_lclk_time[7:0] 0011 1111 3fh 63 5 05h rst_ext_dclk r/w rst_ext_dclk_time[7:0] 0010 0000 20h 32 6 06h dcmsu_prediv r/w dcms u_predivider[7:0] 0001 1110 1eh 30 8 08h ld_pol_lsb r/w ld_pol[7:0] 0000 0000 00h 0 9 09h ld_pol_msb r/w ld_pol[15:8] 0000 0000 00h 0 10 0ah ld_cntrl r/w parityc descramble sel_en[1:0] word_swap ldab_ swap iq_ format edge_ ldclk 0000 0011 03h 3 11 0bh misc_cntrl r/w sr_cdi reserved i_lev_ cntrl[1:0] q_lev_cntrl[1:0] cdi_mode[1:0] 0000 0000 00h 0 12 0ch i_dc_lvl_lsb r/w i_dc_level[7:0] 0000 0000 00h 0 13 0dh i_dc_lvl_msb r/w i _dc_level[15:8] 0100 0000 20h 32 14 0eh q_dc_lvl_lsb r/w q_dc_level[7:0] 0000 0000 00h 0 15 0fh q_dc_lvl_msb r/w q_dc_level[15:8] 0100 0000 20h 32 27 1bh type_id r dac frontend[1:0] dual dsp[1:0] bit_res[1:0] 0011 1010 3ch 60
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 55 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps ; x2, x4 and x8 interpolating 28 1ch dac_version r dac _version_id[7:0] 0000 0001 01h 1 29 1dh dig_version r dig_version_id[7:0] 0000 0001 01h 1 30 1eh ld_version r lvds_ version_id[7:0] 0000 0001 01h 1 31 1fh page_address r/w - - - - - page_add[2:0] 0000 0000 00h 0 table 79. page_0a register allocation map ?continued address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dec
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 56 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10.18.7 page a bit definition detailed description table 80. register main_cntrl (address 00h) default values are shown highlighted. bit symbol access value description 4 ld_pd r/w lvds interface power-down (control possible only when pd_cntrl = 1) 0 switched on 1 switched off 3 pd_cntrl r/w power-down modes controlled by 0 dcmsu block 1 spi registers 2 cal_cntrl r/w compensation delay controlled by 0 dcmsu block (automatic calibration) 1 spi registers (manual control) 1 rst_dclk r/w reset dclk 0 disable 1 enable 0 rst_lclk r/w reset lvds clock 0 disable 1 enable table 81. register man_ldclkdel (address 01h) default values are shown highlighted. bit symbol access value description 3 to 0 ldclk_del[3:0] r/w lvds clock compensation delay (control only if cal_cntrl = 1) - 4-bit compensation delay for lvds clock table 82. register dbg_lvds (address 02h) default values are shown highlighted. bit symbol access value description 3 sber r/w simple ber control 0 no action 1 simple ber active 2 to 0 reserved r/w 000 reserved table 83. register rst_ext_lclk (address 04h) default values are shown highlighted. bit symbol access value description 7 to 0 rst_ext_lclk_time[7:0] r/w specify ext ension time reset, expressed in lvds clock period - 8 bits for the extension time reset
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 57 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 84. register rst_ext_dclk (address 05h) default values are shown highlighted. bit symbol access value description 7 to 0 rst_ext_dclk_time[7:0] r/w specify extension time reset, expressed in dclk period - 8 bits for the extension time reset table 85. register dcsmu_prediv (address 06h) default values are shown highlighted. bit symbol access value description 7 to 0 dcmsu_predivider[7:0] r/w predivider value for the dcmsu, expressed in lvds clock period - 8 bits for the predivider value table 86. register ld_pol_lsb (address 08h) default values are shown highlighted. bit symbol access value description 7 to 0 ld_pol[7:0] r/w toggles polarity of corresponding bit pair within ld[7:0] - most significant 6 bits for the polarity toggle table 87. register ld_pol_msb (address 09h) default values are shown highlighted. bit symbol access value description 7 to 0 ld_pol[15:8] r/w toggles polarity of corresponding bit pair within ld[7:0] - most significant 6 bits for the polarity toggle table 88. register ld_cntrl (address 0ah) default values are shown highlighted. bit symbol access value description 7 parityc r/w parity check 0 disable 1 enable 6 descramble r/w descramble control 0 disable descrambling 1 enable descrambling 5 to 4 sel_en[1:0] r/w ldvs data enable 00 ldvs data enable = align signal from channel a 01 ldvs data enable = align signal from channel b 10 ldvs data enable = 0 11 ldvs data enable = 1 3 word_swap r/w reverse order for lvds path 0 normal operation 1 msb to lsb order reversed
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 58 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 2 ldab_swap r/w swaps lvds a and lvds b paths 0 normal operation 1 lvds a and lvds b paths are swapped 1 iq_format r/w specify iq supplied format 0 folded 1 interleaved 0 edge_ldclk r/w specify sampling edge for lvds data path 0 falling edge of ldclk 1 rising edge of ldclk table 88. register ld_cntrl (address 0ah) ?continued default values are shown highlighted. bit symbol access value description table 89. register misc_cntrl (address 0bh) default values are shown highlighted. bit symbol access value description 7 sr_cdi r/w cdi block software reset control 0 no action 1 perform a software reset on cdi 6 reserved r/w 0 reserved 5 to 4 i_lev_cntrl[1:0] r/w specifi es output from cdi for i path 00 normal operation (cdi data output sent to digital signal processing input) 01 if ldvs data enable = 1, then normal operation; if ldvs data enable = 0, then digital signal processing input = i_dc_level register value 10 digital signal proc essing input = i_dc_level 11 digital signal proc essing input = i_dc_level 3 to 2 q_lev_cntrl[1:0] r/w specifie s output from cdi for q path 00 normal operation (cdi data output sent to digital signal processing input) 01 if ldvs data enable = 1, then normal operation; if ldvs data enable = 0, then digital signal processing input = q_dc_level register value 10 digital signal proc essing input = q_dc_level 11 digital signal proc essing input = q_dc_level 1 to 0 cdi_mode[1:0] r/w specifies cdi mode 00 cdi_mode 0 ( 2 mode) 01 cdi_mode 1 ( 4 mode) 10 cdi_mode 2 ( 8 mode) 11 not used
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 59 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 90. register i_dc_lvl_lsb(address 0ch) default values are shown highlighted. bit symbol access value description 7 to 0 i_dc_level[ 7:0] r/w i_dc_level - least significant 8 bits for i_dc_level table 91. register i_dc_lvl_msb(address 0dh) default values are shown highlighted. bit symbol access value description 7 to 0 i_dc_level[ 15:8] r/w i_dc_level - most significant 8 bits for i_dc_level table 92. register q_dc_lvl_lsb(address 0eh) default values are shown highlighted. bit symbol access value description 7 to 0 q_dc_level[7:0] r/w q_dc_level - least significant 8 bits for q_dc_level table 93. register q_dc_lvl_msb(address 0fh) default values are shown highlighted. bit symbol access value description 7 to 0 q_dc_level[15:8] r/w q_dc_level - most significant 8 bits for q_dc_level table 94. register type_id (address 1bh) default values are shown highlighted. bit symbol access value description 7 dac r calibration 0 uncalibrated device 1 calibrated device 6 to 5 frontend r 01 lvds input interface 4 dual r 0 dual dac 3 to 2 dsp r internal digital signal processing 11 interpolation filter + ssbm 10 ssbm 01 interpolation filter 00 none 1 to 0 bit_res r dac bit resolution 00 16 bits 01 14 bits 10 12 bits 11 10 bits
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 60 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 95. register dac_version (address 1ch) default values are shown highlighted. bit symbol access value description 7 to 0 dac_version_id[7:0] r/w dac version number - 8 bits for the dac version number table 96. register dig_version (address 1dh) default values are shown highlighted. bit symbol access value description 7 to 0 dig_version_id[7:0] r/w digital version number - 8 bits for the digital version number table 97. register dig_version (address 1eh) default values are shown highlighted. bit symbol access value description 7 to 0 lvds_version_id[7:0] r/w l vds receiver version number - 8 bits for the lvds receiver version number table 98. register page_add (address 1fh) default values are shown highlighted. bit symbol access value description 2 to 0 page_add[2:0] r/w page address - current page address
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 61 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 11. package outline fig 30. package outline sot813-3 (hvqfn72) references outline version european projection issue date iec jedec jeita sot813-3 - - - - - - - - - sot813-3_po 10-03-23 10-04-02 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 10.1 10.0 9.9 7.2 7.1 7.0 10.1 10.0 9.9 0.5 8.5 0.5 0.4 0.3 0.1 a dimensions note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. h vqfn72: plastic thermal enhanced very thin quad flat package; no leads; 7 2 terminals; body 10 x 10 x 0.85 mm sot813- 3 a 1 b 0.30 0.21 0.18 cd (1) d h e (1) e h 7.2 7.1 7.0 ee 1 e 2 8.5 lv 0.1 w 0.05 y 0.05 y 1 0 5 10 mm scale terminal 1 index area b a d e c y c y 1 x detail x a c a 1 b e 2 e 1 e e 1/2 e 1/2 e a c b v c w terminal 1 index area d h e h 1 18 19 36 37 54 55 72
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 62 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 12. abbreviations table 99. abbreviations acronym description bw bandwidth bwa broadband wireless access cdi clock domain interface cdma code division multiple access cml current mode logic cmos complementary metal oxide semiconductor dac digital-to-analog converter edge enhanced data rates for gsm evolution fir finite impulse response gsm global system for mobile communications if intermediate frequency imd3 third order intermodulation lmds local multipoint distribution service lo local oscillator lvds low-voltage differential signaling nco numerically controlled oscillator nmos negative metal-oxide semiconductor pll phase-locked loop sfdr spurious-free dynamic range spi serial peripheral interface wcdma wide band code division multiple access wll wireless local loop
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 63 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 13. glossary 13.1 static parameters inl ? ithe deviation of the transfer function from a best fit straight line (linear regression computation). dnl ? the difference between the ideal and the measured output value between successive dac codes. 13.2 dynamic parameters spurious-free dynamic range (sfdr) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. decibels relative to full scale (dbfs) ? unit used in a digital system in order to measure the amplitude level in decibel relative to the maximum peak value. intermodulation distortion (imd) ? from a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products imd2 and imd3 (second order and third order components) are defined below. imd2 ? the ratio between the rms value of either tone and the rms value of the worst second order inter modulation product. imd3 ? the ratio between the rms value of either tone and the rms value of the worst third order inter modulation product. total harmonic distortion (thd) ? the ratio between the rms value of the harmonics of the output frequency and the rms valu e of the output sine wave. usually, the calculation of thd is done on the first 5 harmonics. signal-to-noise ratio (snr) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the noise excluding the harmonics and the dc component. restricted bandwidth spurious-free dynamic range (sfdr rbw ) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the noise, including the harmonics, in a given bandwidth centered around f offset .
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 64 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 14. revision history table 100. revision history document id release date data sheet status change notice supersedes DAC1627D1G25 v.1 20110429 objective data sheet - -
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 65 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 66 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 67 of 69 continued >> nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 17. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 3. limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. thermal characteristics . . . . . . . . . . . . . . . . . . .7 table 5. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 6. read or write mode access description . . . . .13 table 7. number of bytes to be transferred . . . . . . . . . .13 table 8. spi timing characteristic s . . . . . . . . . . . . . . . .14 table 9. input lvds bus swapping . . . . . . . . . . . . . . . .16 table 10. folded and interleaved format mapping . . . . . .17 table 11. compensation delay values for manual tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 12. cdi mode 0: operating modes examples . . . .22 table 13. cdi mode 1: operating modes examples . . . .22 table 14. cdi mode 2: operating modes examples . . . .23 table 15: interpolation filter coeffi cients . . . . . . . . . . . . .24 table 16. complex modulator operation mode . . . . . . . .26 table 17. inversion filter coefficients . . . . . . . . . . . . . . . .27 table 18. dac transfer function . . . . . . . . . . . . . . . . . . .28 table 19. i o(fs) coarse adjustment . . . . . . . . . . . . . . . . . .29 table 20. i o(fs) fine adjustment . . . . . . . . . . . . . . . . . . . .29 table 21. digital offset adjustment . . . . . . . . . . . . . . . . .30 table 22. auxiliary dac transfer function . . . . . . . . . . . .31 table 23. page_00 register allocation map . . . . . . . . . . .38 table 24. register common (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 table 25. register txcfg (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 table 26. register pllcfg (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 table 27. register freqnco_b0 (address 04h) . . . . . .41 table 28. register freqnco_b1 (address 05h) . . . . . .42 table 29. register freqnco_b2 (address 06h) . . . . . .42 table 30. register freqnco_b3 (address 07h) . . . . . .42 table 31. register freqnco_b4 (address 08h) . . . . . .42 table 32. register ph_corr_ctl0 (address 09h) . . . .42 table 33. register ph_corr_ctl1 (address 0ah) . . .42 table 34. register dac_a_dgain_lsb (address 0bh) .42 table 35. register dac_a_dgain_msb (address 0ch) 43 table 36. register dac_b_dgain_lsb (address 0dh) 43 table 37. register dac_b_dgain_msb (address 0eh) 43 table 38. register dac_out_ctrl (address 0fh) . . .43 table 39. register dac_clipping (address 10h) . . . . .43 table 40. register dac_a_offset_lsb (address 11h) . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 41. register dac_a_offset_msb (address 12h) . . . . . . . . . . . . . . . . . . . . . . . . .44 table 42. register dac_b_offset_lsb (address 13h) . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 43. register dac_b_offset_msb (address 14h) . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 44. register phinco_lsb (address 15h) . . . . . . 44 table 45. register phinco_msb (address 16h) . . . . . . 44 table 46. register dac_a_gain1 (address 17h) . . . . . 44 table 47. register dac_a_gain2 (address 18h) . . . . . 44 table 48. register dac_b_gain1 (address 19h) . . . . . 44 table 49. register dac_b_gain2 (address 1ah) . . . . . 45 table 50. dac_a_aux_msb register (address 1bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 51. dac_a_aux_lsb register (address 1ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 52. dac_b_aux_msb register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 53. dac_b_aux_lsb register (address 1eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 54. spi_page register (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 55. page 1 register allocation map . . . . . . . . . . . . 46 table 56. mds_main register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 57. mds_win_period_a register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 58. mds_win_period_b register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 59. mds_misccntrl0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 60. mds_man_adjustdl y register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 61. mds_auto_cycles register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 62. mds_misccntrl1 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 63. mds_offset_dly register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 64. mds_adjdelay register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 65. mds_status0 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 66. mds_status1 register (address 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 67. dac_current_aux register (address 0eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 68. dac_current_0 register (address 0fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 69. dac_current_1 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51
DAC1627D1G25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. objective data sheet rev. 1 ? 29 april 2011 68 of 69 nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating table 70. dac_current_2 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .51 table 71. dac_current_3 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .51 table 72. dac_current_4 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 73. dac_current_5 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 74. dac_current_6 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 75. bias current control table . . . . . . . . . . . . . . . . .52 table 76. dac_pon_sleep register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 77. dac_test_8 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 78. spi_page register (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 79. page_0a register alloca tion map . . . . . . . . . . .54 table 80. register main_cntrl (address 00h) . . . . . .56 table 81. register man_ldclkdel (address 01h) . . . .56 table 82. register dbg_lvds (address 02h) . . . . . . . .56 table 83. register rst_ext_lclk (address 04h) . . . .56 table 84. register rst_ext_dclk (address 05h) . . . .57 table 85. register dcsmu_prediv (address 06h) . . . .57 table 86. register ld_pol_lsb (address 08h) . . . . . . .57 table 87. register ld_pol_msb (address 09h) . . . . . .57 table 88. register ld_cntrl (address 0ah) . . . . . . . .57 table 89. register misc_cntrl (address 0bh) . . . . . .58 table 90. register i_dc_lvl_lsb(address 0ch) . . . . .59 table 91. register i_dc_lvl_msb(address 0dh) . . . . .59 table 92. register q_dc_lvl_lsb(address 0eh) . . . . .59 table 93. register q_dc_lvl_msb(address 0fh) . . . .59 table 94. register type_id (address 1bh) . . . . . . . . . .59 table 95. register dac_version (address 1ch) . . . . .60 table 96. register dig_version (address 1dh) . . . . .60 table 97. register dig_version (address 1eh) . . . . .60 table 98. register page_add (address 1fh) . . . . . . . .60 table 99. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 100. revision history . . . . . . . . . . . . . . . . . . . . . . . .64
nxp semiconductors DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 29 april 2011 document identifier: DAC1627D1G25 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 thermal characteristics . . . . . . . . . . . . . . . . . . 7 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 application information. . . . . . . . . . . . . . . . . . 12 10.1 general description . . . . . . . . . . . . . . . . . . . . 12 10.2 serial peripheral interfac e (spi) . . . . . . . . . . . 13 10.2.1 protocol description . . . . . . . . . . . . . . . . . . . . 13 10.2.2 spi timing description . . . . . . . . . . . . . . . . . . . 14 10.3 power-on sequence . . . . . . . . . . . . . . . . . . . . 14 10.4 lvds data input format (dif) block . . . . . . . 15 10.4.1 input port polarity . . . . . . . . . . . . . . . . . . . . . . 15 10.4.2 input port mapping . . . . . . . . . . . . . . . . . . . . . 16 10.4.3 input port swapping . . . . . . . . . . . . . . . . . . . . 16 10.4.4 input port formatting . . . . . . . . . . . . . . . . . . . . 17 10.5 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.5.1 lvds ddr clock. . . . . . . . . . . . . . . . . . . . . . . 18 10.5.2 dac core clock . . . . . . . . . . . . . . . . . . . . . . . . 18 10.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.7 operating modes . . . . . . . . . . . . . . . . . . . . . . 21 10.7.1 cdi mode 0 (x2 interpolation). . . . . . . . . . . . . 22 10.7.2 cdi mode 1 (x4 interpolation). . . . . . . . . . . . . 22 10.7.3 cdi mode 2 (x8 interpolation). . . . . . . . . . . . . 23 10.8 fir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.9 single sideband modula tor (ssbm). . . . . . . . 25 10.9.1 nco in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 25 10.9.2 nco low power . . . . . . . . . . . . . . . . . . . . . . . 26 10.9.3 complex modulator . . . . . . . . . . . . . . . . . . . . 26 10.9.4 minus 3db. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.10 inverse sinx / x . . . . . . . . . . . . . . . . . . . . . . . . 27 10.11 dac transfer function . . . . . . . . . . . . . . . . . . . 27 10.12 full-scale current . . . . . . . . . . . . . . . . . . . . . . 28 10.12.1 regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.12.2 full-scale current adjustment . . . . . . . . . . . . . 28 10.13 digital offset adjustment . . . . . . . . . . . . . . . . . 29 10.14 analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.15 auxiliary dacs . . . . . . . . . . . . . . . . . . . . . . . . 31 10.16 output configuration . . . . . . . . . . . . . . . . . . . . 32 10.16.1 basic output configuration . . . . . . . . . . . . . . . 32 10.16.2 iq-modulator - bgx7100 interface . . . . . . . . 33 10.16.3 iq-modulator - dc interface. . . . . . . . . . . . . . 33 10.16.4 iq-modulator - ac interface . . . . . . . . . . . . . . 36 10.17 design recommendations . . . . . . . . . . . . . . . 36 10.17.1 power and grounding. . . . . . . . . . . . . . . . . . . 36 10.18 configuration interface. . . . . . . . . . . . . . . . . . 37 10.18.1 register description . . . . . . . . . . . . . . . . . . . . 37 10.18.2 page 0 register allocation map . . . . . . . . . . . 38 10.18.3 page 0 bit definition detailed description . . . . 40 10.18.4 page 1 allocation map . . . . . . . . . . . . . . . . . . 46 10.18.5 page 1 bit definition detailed description . . . . 48 10.18.6 page a register allocation map . . . . . . . . . . . 54 10.18.7 page a bit definition detailed description . . . . 56 11 package outline. . . . . . . . . . . . . . . . . . . . . . . . 61 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 62 13 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 63 13.2 dynamic parameters . . . . . . . . . . . . . . . . . . . 63 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 64 15 legal information . . . . . . . . . . . . . . . . . . . . . . 65 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 65 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 66 16 contact information . . . . . . . . . . . . . . . . . . . . 66 17 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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